View 74F28304_1202084.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

74F283 4-Bit Binary Full Adder with Fast Carry
April 1988 Revised January 2004
74F283 4-Bit Binary Full Adder with Fast Carry
General Description
The 74F283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words (A0-A3, B0-B3) and a Carry input (C0). It generates the binary Sum outputs (S0-S3) and the Carry output (C4) from the most significant bit. The 74F283 will operate with either active HIGH or active LOW operands (positive or negative logic).
Ordering Code:
Order Number 74F283SC 74F283PC Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Logic Symbols
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Pin Names A0-A3 B0-B3 C0 S0-S3 C4 Description A Operand Inputs B Operand Inputs Carry Input Sum Outputs Carry Output U.L. Input IIH/IIL 20 A/-1.2 mA 20 A/-1.2 mA 20 A/-0.6 mA HIGH/LOW Output IOH/IOL 1.0/2.0 1.0/2.0 1.0/1.0 50/33.3 50/33.3
-1 mA/20 mA -1 mA/20 mA
(c) 2004 Fairchild Semiconductor Corporation
DS009513
www.fairchildsemi.com
74F283
Functional Description
The 74F283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (S0-S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. 20 (A0 + B0 + C0) + 21 (A1 + B1) However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the 74F283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1- I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs I1-I5 are true, the output M5 is true.
+ 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4
Where (+) = plus Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the 74F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure 1. Note that if C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic. Due to pin limitations, the intermediate carries of the 74F283 are not brought out for use as inputs or outputs. C0 Logic Levels Active HIGH Active LOW
Active HIGH: 0 + 10 + 9 = 3 + 16
A0 L 0 1
A1 H 1 0
A2 L 0 1
A3 H 1 0
B0 H 1 0
B1 L 0 1
B2 L 0 1
B3 H 1 0
S0 H 1 0
S1 H 1 0
S2 L 0 1
S3 L 0 1
C4 H 1 0
L 0 1
Active LOW: 1 + 5 + 6 = 12 + 0
FIGURE 1. Active HIGH versus Active LOW Interpretation
FIGURE 2. 3-Bit Adder
FIGURE 3. 2-Bit and 1-Bit Adders
FIGURE 4. 5-Input Encoder
FIGURE 5. 5-Input Majority Gate
www.fairchildsemi.com
2
74F283
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
74F283
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current Power Supply Current -60 36 36 4.75 3.75 -0.6 -1.2 -150 55 55 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A mA mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (CO) VIN = 0.5V (An, Bn) VOUT = 0V VO = HIGH VO = LOW
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay C0 to Sn Propagation Delay An or Bn to Sn Propagation Delay C0 to C4 Propagation Delay An or Bn to C4 3.5 3.0 3.0 3.0 3.0 3.0 3.0 2.5 VCC = +5.0V CL = 50 pF Typ 7.0 7.0 7.0 7.0 5.7 5.4 5.7 5.3 Max 9.5 9.5 9.5 9.5 7.5 7.0 7.5 7.0 TA = -55C to +125C VCC = 5.0V CL = 50 pF Min 3.5 3.0 3.0 3.0 3.0 2.5 3.0 2.5 Max 14.0 14.0 17.0 14.0 10.5 10.0 10.5 10.0 TA = 0C to +70C VCC = 5.0V CL = 50 pF Min 3.5 3.0 3.0 3.0 3.0 3.0 3.0 2.5 Max 11.0 11.0 13.0 11.5 8.5 8.0 8.5 8.0 ns ns ns ns Units
www.fairchildsemi.com
4
74F283
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
5
www.fairchildsemi.com
74F283 4-Bit Binary Full Adder with Fast Carry
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

▲Up To Search▲

Price & Availability of 74F28304

	To Download 74F28304 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .